Zed Audio Ra Betriebsanweisung

ZedBoard (Zynq™ Evaluation and Development) Hardware User’s Guide Version 2.0 2 October 2013

02-Oct-2013 9 Two packages can be used on the ZedBoard; SO-16 and WSON. For the WSON package, there is a heat sink slug under the package that is

02-Oct-2013 10 2.2.3 SD Card Interface The Zynq PS SD/SDIO peripheral controls communication with the ZedBoard SD Card (A 4GB Class 4 card is inc

02-Oct-2013 11 2.3 USB 2.3.1 USB OTG Warning: After the design of the ZedBoard was complete, a timing incompatibility between the TUSB1210 PHY an

02-Oct-2013 12 The UART 1 Zynq PS peripheral is accessed through MIO[48:49] in MIO Bank 1/501 (1.8V). Since the CY7C64225 device requires either

02-Oct-2013 13 2.3.4 USB circuit protection All USB data lines, D+/-, are protected with a TE SESD0402Q2UG-0020-090. Figure 8 – ESD Protection

02-Oct-2013 14 Table 7 - HDMI Interface Connections Signal Name Description Zynq pin ADV7511 pin HDP Hot Plug Detect signal input N/C 30 HD-INT Int

02-Oct-2013 15 Figure 9 - HDMI Video Interface Timing The HDMI transmitter connects externally via a HDMI Type A connector, J9, TE 1903015-1. Ci

02-Oct-2013 16 2.4.2 VGA Connector The ZedBoard also allows 12-bit color video output through a through-hole VGA connector, TE 4-1734682-2. Each

02-Oct-2013 17 2.4.3 I2S Audio Codec An Analog Devices ADAU1761 Audio Codec provides integrated digital audio processing to the Zynq-7000 AP SoC.

02-Oct-2013 18 2.4.4 OLED An Inteltronic/Wisechip UG-2832HSWEG04 OLED Display is used on the ZedBoard. This provides a 128x32 pixel, passive-mat

02-Oct-2013 1 Table of Contents 1 INTRODUCTION ...

02-Oct-2013 19 2.6.2 Program Push Button Switch A PROG push switch, BTN6, toggles Zynq PROG_B. This initiates reconfiguring the PL-subsection by t

02-Oct-2013 20 2.7.3 User LEDs The ZedBoard has eight user LEDs, LD0 – LD7. A logic high from the Zynq-7000 AP SoC I/O causes the LED to turn on.

02-Oct-2013 21 Table 15 – Ethernet PHY Pin Assignment and Definitions Signal Name Description Zynq pin MIO 88E1510 pin RX_CLK Receive Clock A14 16

02-Oct-2013 22 2.9.2 Digilent Pmod™ Compatible Headers (2x6) The ZedBoard has five Digilent Pmod™ compatible headers (2x6). These are right-angle

02-Oct-2013 23 Table 16 - Pmod Connections Pmod Signal Name Zynq pin Pmod Signal Name Zynq pin JA1 JA1 Y11 JB1 JB1 W12 JA2 AA11 JB2 W11 JA3 Y10 JB

02-Oct-2013 24 The ZedBoard AMS header is comparable with similar connectors on the Xilinx KC705 and ZC702 boards. Any AMS plug-in cards built for

02-Oct-2013 25 Table 17 - Analog Header Pin Out Name Description Requirement XADC Header Zynq Pin VP/VN Two pins required. Dedicated pins on the

02-Oct-2013 26 2.10 Configuration Modes Zynq-7000 AP SoC devices use a multi-stage boot process that supports both non-secure and secure boot (note

02-Oct-2013 27 The PS boot mode selections are shown in the table below, default setting highlighted in yellow: Table 18 – ZedBoard Configuration

02-Oct-2013 28 ZedBoard automatically adds the FMC into the JTAG chain when an FMC card is plugged into the board via the FMC-PRSNT signal. 2.11 Po

02-Oct-2013 2 1 Introduction The ZedBoard is an evaluation and development board based on the Xilinx ZynqTM-7000 All Programmable SoC (AP SoC). Co

02-Oct-2013 29 The table below shows the minimum required voltage rails, currents, and tolerances. Table 19 - TPS65708 Connections Voltage (V) C

02-Oct-2013 30 2.11.5 Power Good LED A green status LED, LD13, indicates when power is good on the board. Power Good is wired with the Resets and

02-Oct-2013 31 2.11.7 Testing The power circuitry has been tested to verify compliance with the Zynq power requirements, such as: • Tolerance o

02-Oct-2013 32 3 Zynq-7000 AP SoC Banks The following figure and table show Zynq CLG484 I/O bank assignments on the Zynq board. Figure 19 - Zyn

02-Oct-2013 33 3.1 Zynq-7000 AP SoC Bank Voltages Table 21 - Zynq Bank Voltage Assignments PS-Side Bank Voltage (default) MIO Bank 0/500 3.3V M

02-Oct-2013 34 4 Jumper Settings Table 22 - Jumper Settings Ref Designator Description Default Setting Function JP1 Microphone Input Bias Open

02-Oct-2013 35 Figure 20 - ZedBoard Jumper Map

02-Oct-2013 36 5 Mechanical The ZedBoard measures 6.3”x6.3”. Figure 21 - ZedBoard Mechanical

02-Oct-2013 37 Revision History Rev date Rev # Reason for change 8/1/12 1.0 Initial ZedBoard User’s Guide 8/2/12 1.1 Mapped Configuration Mode T

02-Oct-2013 3 Figure 1 – ZedBoard Block Diagram

02-Oct-2013 4 1.1 Zynq Bank Pin Assignments The following figure shows the Zynq bank pin assignments on the ZedBoard followed by a table that show

02-Oct-2013 5 2 Functional Description 2.1 All Programmable SoC The ZedBoard features a Xilinx Zynq XC7Z020-1CLG484 All Programmable SoC (AP SoC)

02-Oct-2013 6 The PCB design guidelines outlined in Zynq datasheet must be followed for trace matching, etc. Table 1 - DDR3 Connections Signal Nam

02-Oct-2013 7 Table 2 - DDR3 Worksheet Calculations Pin Group Length (mm) Length (mils) Package Length (mils) Total Length (mils) Propagation Dela

02-Oct-2013 8 The relevant device attributes are: • 256Mbit • x1, x2, and x4 support • Speeds up to 104 MHz, supporting Zynq configuration rates